Full-width arrays comprised of adjoined or butted semiconductor chips are increasingly common for scanning, imaging, and printing applications. Such full-width arrays are used as printheads in ink jet printing, monochrome and color scanner bars, and, for some applications, digital image capture applications.
A typical full-width array is comprised of a series of discrete chips butted or otherwise adjoined in order to obtain the appropriate length necessary to cover a “full-width”. For many printing applications, such “full-width” is 11 inches or more in order to enable printing or scanning of standard 8.5×11 B4 paper. When edge butted together, such chips form an imaging bar of the desired length. Such a bar is rigidly mounted into a bar fixture having appropriate electrical contacts and features appropriate for mounting and electrically connecting the entire full-width assembly to the equipment into which it is placed. While monochrome imaging bars require only one row of sensing elements, color imaging bars are provided with at least three different color filters, such as red, green and blue, overlying three or more rows of closely spaced light sensor elements (photo-sites), to provide electrical output signals corresponding to the colors of the document image being scanned. Details of typical full-width color scanning arrays are taught by patents such as U.S. Pat. Nos. 5,808,297, 5,543,838, 5,550,663, 5,604,362, and 5,519,514,all of which are hereby incorporated herein by reference.
Typical fabrication of a full-width array is explained in relation to FIGS. 1–3. Referring first to FIG. 1, a silicon wafer 10 is shown with discrete chips formed thereon. For exemplary purposes, several discrete chips are labeled 11 although, as indicated in FIG. 1, hundreds of chips are formed on the same silicon wafer. The blackened edge regions represent chips that must be discarded due to known edge defects. Formation of the wafer and the chips is pursuant well-known semiconductor techniques. For applications such as full-color scanner, colorimeter, and other imaging applications, portions of each chip may be coated while in situ on the wafer with various filters in order to render portions of the chip sensitive to various wavelengths. The wafer can be of any size, and wafer sizes of 5 inches and more are now standard in the industry.
Referring to FIG. 2, a close-up of an individual chip 11 is shown. Such chip is for a scanner array, but those skilled in the art will recognize that the embodiments described herein apply to a wide range of chips, especially those to be formed into full-width arrays. In the orthogonal elevated view of FIG. 2, 4 rows of sensor pixels are shown in region 12. Row 13 has no light filter on top of it and is accordingly optimized for monochrome sensing. Filters are coated on the other three rows while in situ on the wafer. The filters optimize each of the three rows identified as 14 for red, green blue, respectively, or for some other color space such as cyan, yellow, and magenta. With such filters, chip 11 can serve as a monochrome scanner and as a process color scanner. Chip 11 contains much internal circuitry (not shown). Interface with chip 11 is accomplished through the various contact points, or pads, shown in region 15. Input and output through various of these pads controls the timing configuration, power requirements, and data inputs and outputs required for the chip to capture and then transmit its scanning data. In the embodiment of a full-width array chip 11 shown, each of the pads measures approximately 0.004 inches by 0.007 inches.
Referring again to FIG. 1, it is possible and standard in the art to test each discrete chip 11 while in situ on the wafer. To do so, the temperature of the wafer is elevated to between about 50 and about 60 degrees centigrade. Once the temperature is elevated, each pad 15 of the chip undergoing testing must be located and contacted simultaneously. The precision required to locate and simultaneously place a test probe on each of the 15 or more pads per chip (18 are shown in FIG. 2), in turn requires an automated vision system for efficient manufacturing. Companies such as Cognex Corporation make suitable machine vision system. When dies are regularly spaced in situ on a wafer such as shown in FIG. 1, a machine vision system can operate by finding the precise location of positioning markings on the wafer. Once these markings are determined, then each of the dies on the wafer and each of the pads on the dies become known. Once the location of the pads are mapped into an X-Y grid by the vision system, the map can be passed to a test probe system such as those made by Electroglas, Inc. The test probe system uses the X-Y map to find and test the appropriate pads. Generally, the probe itself remains stationary while the wafer, mounted on a stage, is raised and lowered in a step and repeat fashion until all eligible die on the wafer have been tested.
One complication to the above test procedure is that even small amounts of oxide on the pads may hinder good electrical contact. To avoid false negative results due to poor electrical contact between the pads and the probe, the probe is designed to move in a scraping or scrubbing motion over the pads in order to scrape oxides from the pads and to thereby enhance electrical contact. The intended result is that each chip 11 can be reliably tested while within the wafer. The location of defective chips is recorded, and after cutting the chips from the wafer, defective chips are discarded in a sorting process.
The cutting process of a wafer may involve processes including attaching a UV release film to the face of the wafer in order that it can be flipped and score cut from the reverse side. The UV film is then cured with UV exposure to facilitate its non-destructive removal. The wafer is then turned again and placed on nittotape to stabilize it while it is through cut from the front side within a film frame. After through cutting, the discrete dies, or chips, are sorted by being picked from the nittotape, transported, and placed into a storage tray, or wafflepack, and stored until assembled into a final product.
Although the present invention applies to a wide variety of dies cut from wafers, it is explained in particular in relation to dies, or chips, intended for fabrication into full-width imaging arrays. Manufacture of a full-width array from discrete chips 11 involves selection of a required number of chips, aligning such chips precisely in a fixture (generally in a line), and permanently fastening the butted and adjoining chips within the fixture. The full-width array is then completed by routing appropriate wires from the pads in region 15 to the appropriate input/output ports of the full-width array and by affixing to the assembly any other mechanical or electrical features needed for operation. For imaging-related chips such as the one shown in FIG. 2 that measure about 16 millimeters long by about 1.0 millimeters wide, approximately 20 chips per array are assembled into a full-width array.
The simplified manufacturing process above is conventional in the art. Closer focus on the process of cutting the chips from the wafer and placing them in the finished array reveals that a significant number of defects in chips are created during the process that cuts the wafer and then during the process that handles, or sorts, the discrete chips after they have been cut from the wafer.
Referring to FIG. 3, a discrete die holding tray of the prior art, sometimes called a “wafflepack”, is shown. This wafflepack 16 is used to hold, store, and transport chips such as chips 11 after the chips have been cut from wafer 10. Wafflepack 16 is typically made of a rigid molded plastic such as PVC, ABS, styrene or any similar rigid, non-conductive material. Once cut and sorted, discrete chips 11 are placed within the hundreds of pockets 17 located on each wafflepack. Each pocket has a length dimension and a width dimension corresponding to the comparable dimensions of chips 11. Such die holding trays are made by a number of manufacturers including Entegris, Inc., which markets such trays under the trademark Fluoroware®. The wafflepack shown in FIG. 3 is similar to one of the Fluoroware H44 series of wafflepack trays.
Advantages of the prior art wafflepack include low cost and durability. For its intended purpose of holding, storing, and transporting chips, the wafflepack of the prior art is very adequate. However, it would be desirable to be able to test individual die chips while placed in the wafflepack in order to identify those chips that became defective during the cutting and sorting processes that preceded placement into the wafflepack. Currently, there is no effective means to test each die chip 11 from the time at which it is cut from the wafer until it is assembled into a finished full-width array. The result is that a significant number of assembled full-width arrays are initially assembled with one or more defective chips. At a minimum, these need to be expensively reworked in order to remove the defective chips and insert nominal chips. Worse, some number of full-width arrays are not successfully re-worked, and these arrays must be discarded in their entirety.
Although discrete chips may individually be tested by placement on a test fixture, such discrete chips cannot adequately be tested en masse while placed in storage fixtures such as wafflepacks of the prior art for reasons related to the precision necessary to find the tiny pads 15 and to the stability necessary for the probes to scrape and then maintain electrical contact with the pads. In a conventional plastic wafflepack, the backplate of the wafflepack is not reliably flat. Even slight warpness along the length dimension of chips 11 causes the chip to rock and lose contact with the probes, especially during the scraping operation. Such warpness in the molded plastic is extremely common due to differential curing or molding of the plastic and due to stresses introduced by the structural features of the wafflepack such as raised relief ribbing, etc. Additionally, it is difficult or impossible to eliminate at least a small radius between the bottom and the sidewalls of each pocket 17 using a molding process with plastic. Similarly, molded plastic does not yield precision along the width dimension. The pockets must be wide enough to accept each chip yet any excess width allows the chip to “wiggle” along its width dimension when probed. The result is that each chip can “wiggle” along its width dimension when probed, thereby losing contact between the pads and the probe. Thus, conventional wafflepacks of the prior art cannot hold chips such as chips 11 firmly enough in all axes to enable solid contact between the probe and the tiny pads during the scraping action of the pad and during the testing itself.
It would be desirable to design and manufacture a die storage tray or wafflepack that positions and holds discrete dies in a stable fashion sufficient to permit testing while held in a wafflepack. It would also be desirable to create a test procedure enabling die testing while held in such a wafflepack.
One embodiment of the present invention is a method for testing dies, comprising: placing a plurality of dies in a die holding tray; mounting the holding tray to a mounting stage of an imaging and testing apparatus; drawing a partial vacuum through channels communicating between the bottom of die pockets in the die holding tray and a vacuum source; using an automated vision system to map the position of dies held in the holding tray; with the use of the map, moving the mounting stage in relation to a test probe to the approximate position of an individual die held in the holding tray; skewing the mounting stage in relation to the test probe to align the probe with the pads of the die; contacting the pads with a test probe; and testing the die with the test probe by sending and receiving electrical signals.
Another embodiment of the present invention is a method for testing dies, comprising: placing a plurality of dies in a die holding tray; mounting the holding tray to a mounting stage of an imaging and testing apparatus; drawing a partial vacuum through channels communicating between the bottom of die pockets in the die holding tray and a vacuum source; using an automated vision system to map the position of dies held in the holding tray; with the use of the map, moving the mounting stage in relation to a test probe to align the probe with the pads of the die; contacting the pads with a test probe; and testing the die with the test probe by sending and receiving electrical signals.